Job Summary:
Own end-to-end digital design of high-speed, low-power IPs/SoCs, including micro-architecture, RTL coding, synthesis, and timing closure. Work closely with verification, physical design, and DFT teams to ensure first-pass silicon success. Identify and resolve design challenges while optimizing for performance, area, and power.
Key Responsibilities:
• Define micro-architecture and lead RTL design for complex digital blocks or subsystems.
• Own end-to-end design flow including RTL development, synthesis, and timing closure.
• Collaborate with verification, physical design, DFT, and system teams to ensure design quality and first-pass silicon success.
• Review code, drive design best practices, and ensure adherence to coding and design methodologies.
• Debug and resolve functional, timing, and power-related issues across the design lifecycle.
• Optimize designs for performance, power, and area (PPA).
• Mentor junior engineers and provide technical leadership within the team.
• Support silicon bring-up, validation, and post-silicon debug activities.
Required Qualifications (Must Have):
• Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
• 15+ years of experience in digital design/RTL development within the semiconductor industry.
• Strong expertise in micro-architecture definition and RTL design using Verilog/System Verilog.
• Solid understanding of digital design fundamentals, including synchronous design, clock domain crossing (CDC), and low-power design techniques.
• Hands-on experience with synthesis, static timing analysis (STA), and timing closure.
• Familiarity with ASIC/SoC design flows, from specification to silicon bring-up.
• Experience working with cross-functional teams including verification, physical design, and DFT.
• Strong debugging and problem-solving skills across simulation and silicon.
• Proficiency with industry-standard EDA tools (e.g., Synopsys, Cadence, or equivalent).
Preferred Qualifications (Nice to have):
• Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
• Experience with advanced technology nodes (e.g., 7nm, 5nm, or below).
• Proven track record of leading complex SoC/IP development or tape-outs.
• Familiarity with low-power design methodologies (UPF/CPF) and power optimization techniques.
• Exposure to DFT concepts (scan, BIST) and design for testability considerations.
• Experience with high-speed interfaces (e.g., PCIe, DDR, Ethernet) or domain-specific architectures (CPU, GPU, AI/ML accelerators).
• Knowledge of scripting/programming (Python, Perl, Tcl) for design automation and flow improvement.
• Strong understanding of verification methodologies (e.g., UVM) and collaboration with verification teams.
• Experience with emulation, FPGA prototyping, or post-silicon validation.
• Demonstrated technical leadership, mentoring, and ability to drive cross-functional initiative
Key Skills & Competencies:
• Strong problem-solving and debugging mindset for complex design issues
• Ability to drive end-to-end ownership and deliver high-quality results
• Effective collaboration across cross-functional engineering teams
• Clear communication and technical articulation skills
• Mentorship and technical leadership capability
• Adaptability in a fast-paced, high-complexity environment
Additional Information:
• General Shift (9.30am to 6.30pm), flexible environment and the working hours can be tailor made to fit into the requirement of the Business Unit.
• Onsite working: All 5 days from office
Location
Bengaluru
Type
Full-Time
Status
Open
